Thin film capacitors are often fabricated as integral parts of integrated circuits. In order to keep cost to a minimum, every attempt is made to form such capacitors using the same (or almost the same) processing steps that would have been used if the circuit had contained no capacitors, changes in the process being thus largely limited to modification of one or two masks.
A typical sequence of events starts, as illustrated schematically in FIG. 1, with silicon substrate 1 having a layer of gate oxide 2 and regions of field oxide (FOX). Polysilicon layer 3 has been deposited onto the layers of gate oxide and field oxide and then patterned and etched, using standard photolithographic techniques to form gate pedestal 4 which is centrally located between two regions of field oxide.
After removing gate oxide that was not covered by the gate pedestal, source and drain regions 7 were formed below the openings in the gate oxide layer. Additionally, insulating spacers 8 were formed on all exposed vertical walls of polysilicon.
This is followed by a self-aligned silicide (SALICIDE) process which enables precise contact to be made to only the polysilicon layers and not to any insulating areas (such as the spacers or the FOX). The SALICIDE process, as illustrated in FIG. 2, begins with the deposition of silicide forming metal layer 21, such as titanium or cobalt. This is then given an RTA (rapid thermal anneal) of between about 25 and 35 seconds at between about 700 and 750.degree. C. (for titianium; for cobalt the temperature would be between about 500 and 550.degree. C.). This causes a rapid reaction between the metal 21 and the polysilicon areas 3 and 4, but not between the metal and the insulating areas 8 or the FOX, where the metal remains in its original, unreacted form. Thus, when a selective etchant, such as a solution of ammonia, nitric acid, and hydrogen peroxide is used, all unreacted metal gets removed and, as shown in FIG. 3, silicide material 31 is left behind only where there had previously been polysilicon (such as at 3 and 4).
A second RTA is normally given at this stage. This is usually at a temperature between about 850 and 900.degree. C. (for titanium; between about 650 and 750.degree. C. for cobalt) for between about 25 and 35 seconds and is for the purpose of bringing about a phase change in the silicide, whereby a different crystal structure is formed that has a significantly lower resistivity than the structure resulting from the intial reaction between the metal and the silicon.
The next step, assuming a capacitor in series with the gate is required, is to deposit a dielectric layer. Typically, in the prior art, silicon oxynitride or PE (plasma enhanced) oxide has been used for this. This is patterned and etched so that it covers only the gate pedestal (plus any other conductive regions set aside for the formation of additional capacitors). It is shown as layer 41 in FIG. 4. Finally, the upper, or counter, electrode for the capacitor must be formed. Since the usual next step, even if no capacitor was being formed, would be the deposition of a layer of polysilicon (so-called second poly) it has been the standard practice to use this same polysilicon layer for the capacitor's upper electrode (shown as 42 in FIG. 4).
While a capacitor structure of the type illustrated in FIG. 4 represents what is probably the cheapest way to incorporate a capacitor within an integrated circuit, capacitors formed in this way do suffer from certain disadvantages. In particular, they tend to have a large V.sub.cc (voltage coefficient of capacitance) because a depletion layer (that widens with applied voltage) forms in the polysilicon, causing the capacitance to decrease with applied voltage. This is illustrated in FIG. 5 where curve 55 shows the effects of applied voltage (both positive and negative) on a capacitor of this type (i.e. MiP or metal-insulator-poly, the silicide layer being a metal in terms of its electrical behavior). This is a serious drawback in circuits such A-D and D-A converters, for example.
A number of variations on the above capacitor structure have been described in the prior art. For example, Paterson et al. (U.S. Pat. No. 5,108,941 April 1992) describe a capacitor having a polysilicon lower electrode and a metallic (titanium/tungsten) upper electrode. Radosevitch et al. (U.S. Pat. No. 5,576,240 November 1996) describe a capacitor having a lower electrode of titanium nitride on polysilicon and an upper electrode of aluminum.
Kaya et al. (U.S. Pat. No. 5,130,267 July 1992) disclose a capacitor having a lower electrode of polysilicon and an upper electrode of titanium nitride or titanium tungsten. A feature of the invention is that the top plate is split. Mihara et al. (U.S. Pat. No. 5,466,629) teach a structure having a ferroelectric dielectric and a variety of materials for the end plates.
Sandhu et al. (U.S. Pat. No. 5,506,166 April 1996) show a storage cell capacitor having a lower electrode of titanium silicide while an oxidation resistant conductive material, such as a refractory metal, a conductive metal oxide, or a metal nitride, forms the upper electrode. McDonald (U.S. Pat. No. 5,037,772 August 1991) describes a capacitor having having upper and lower electrodes of polysilicon. The capacitor described by Hsu et al. (U.S. Pat. No. 5,338,701 August 1994) is a polycide to polysilicon device.
Hsu et al. (U.S. Pat. No. 5,554,558 September 1996) also describe a polycide to polysilicon device while Paterson (U.S. Pat. No. 4,697,330 October 1987) teaches a polysilicon to polysilicon structure. Finally, Tigelaar et al. (U.S. Pat. No. 4,971,924 November 1990) disclose a metal to polysilicon capacitor.
Thus, there does not appear to be any teaching in the prior art concerning the fabrication of a polycide to polycide capacitor, particularly as part of a process for the manufacture of an integrated circuit.